The present invention relates to a MOS-type solid-state imaging device and, more particularly, to a solid-state imaging device for imaging a plurality of frames at high speeds.
A conventional MOS-type solid-state imaging device has a structure as shown in FIG. 3. This solid-state imaging device, formed by a semiconductor fabricating process, includes a light receiving region 1, a vertical scanning circuit 2 and a horizontal scanning circuit 3 for reading pixel signals.
The light receiving region 1 will be described first. A plurality of n.sup.+ -type impurity regions are embedded in matrix form in a p-type well layer arranged on a surface portion of an n-type semiconductor substrate forming a plurality of photodiodes P.sub.11, P.sub.12, . . . , P.sub.21, P.sub.22, . . . , P.sub.31, P.sub.32, . . . , as shown in FIG. 3. Signal read lines S.sub.1, S.sub.2, S.sub.3, S.sub.4, . . . and vertical scanning lines V.sub.1, V.sub.2, V.sub.3, . . . extend vertically and horizontally, respectively, between these photodiodes. The vertical scanning lines V.sub.1, V.sub.2, V.sub.3, . . . are connected to predetermined bit output contacts b.sub.1, b.sub.2, b.sub.3, . . . of the vertical scanning circuit 2 which is formed of shift registers. The signal read lines S.sub.1, S.sub.2, S.sub.3, S.sub.4, . . . are connected to an output terminal 4 through second switching transistors M.sub.1 , M.sub.2, M.sub.3, M.sub.4, . . . . The gate contacts of the second switching transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4, . . . are connected to predetermined bit output contacts h.sub.1, h.sub.2, h.sub.3, h.sub.4 . . . of the horizontal scanning circuit 3, also formed of shift registers.
A first switching transistor is interposed between each photodiode and its corresponding signal read line, as exemplified by a switching transistor C.sub.1 between the photodiode P.sub.11 and the signal read line S.sub.1. The gate contacts of these first switching transistors are connected to the vertical scanning lines V.sub.1, V.sub.2, V.sub.3, . . . extending from the vertical scanning circuit 2.
To form an image with the MOS-type solid-state imaging device thus constructed, an image is read by scanning at timings as shown in FIG. 4. That is, after receiving an optical image within a predetermined exposure period, a high-level signal S.sub.V1 is applied from the first bit output contact b.sub.1 of the vertical scanning circuit 2 for a predetermined period T, thereby turning on a group of switching transistors connected to the first vertical scanning line V.sub.1. Therefore, the pixel signals corresponding to the photodiodes P.sub.11, P.sub.12, . . . connected to the first vertical scanning line V.sub.1 can be transmitted to the signal read lines S.sub.1, S.sub.2, S.sub.3, S.sub.4, . . . . In addition, within the same period T, a pulse signal S.sub.h is applied from the lower to higher bits of the horizontal scanning circuit 3 at a predetermined period .tau., causing the second switching transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4, . . . to conduct sequentially s that the pixel signal of each of the photodiodes P.sub.11, P.sub.12, . . . will be outputted to the output terminal 4 as a periodic signal S(.tau.) every period .tau..
Then, a high level signal S.sub.V2 is applied from the second bit output contact b: of the vertical scanning circuit 2 for the predetermined period T, thereby turning on a group of second switching transistors connected to the first vertical scanning line V.sub.2. Therefore, the pixel signals corresponding to the photodiodes P.sub.21, P.sub.22, . . . connected to the second vertical scanning line V.sub.2 can be transmitted to the signal read lines S.sub.1, S.sub.2, S.sub.3, S.sub.4, . . . . In addition, within the same period T, the pulse signal S.sub.h is applied from the lower to higher bits of the horizontal scanning circuit 3 at the predetermined period .tau. causing the second switching transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4, . . . to conduct sequentially so that the pixel signal of each of the photodiodes P.sub.21, P.sub.22, . . . will be outputted to the output terminal 4 as the signal S(.tau.) every period .tau..
By repeating the above-described vertical and horizontal scanning operations for the remaining photodiodes, pixel signals equivalent to a single frame are read as a signal S(.tau.).
The above MOS-type solid-state imaging device is adapted for reading pixel signals when a comparatively small number of pixels are scanned at a comparatively low speed. However, if a solid-state imaging device has a large number of pixels (photodiodes), and a large number of pixel signals must be read by the above vertical and horizontal scanning operations, then a very high speed horizontal scanning circuit is necessary, which is not technically feasible in the above imaging device.
To overcome this problem, the inventors of the present invention have researched and developed a solid-state imaging device that can horizontally scan simultaneously a set of plural pixels. This allows the solid-state imaging device to read an image at high speeds without requiring high speed horizontal scanning circuits.
A typical structure of such a solid-state imaging device will be described with reference to FIG. 5. In FIG. 5, reference numeral 2 designates a vertical scanning circuit consisting of shift registers, and reference number 3 designates a horizontal scanning circuit consisting of shift registers. Bit outputs b.sub.1, b.sub.2, . . . b.sub.n of the vertical scanning circuit 2 are connected to vertical scanning lines V.sub.1, V.sub.2, . . . V.sub.n, respectively, while bit outputs h.sub.1, h.sub.2, . . . h.sub.m of the horizontal scanning circuit 3 are connected to horizontal scanning lines l.sub.1, l.sub.2, . . . l.sub.m, respectively.
Further, a group of photodiodes, each of which forms a pixel, are connected, in a manner similar to that shown in FIG. 3, to predetermined signal read lines S.sub.1, S.sub.2, . . . S.sub.16m, respectively, through switching transistors. The switching transistors conduct or do not conduct in accordance with the voltage of each of the vertical scanning lines V.sub.1, V.sub.2, . . . V.sub.n, while predetermined switching transistors M.sub.11 -M.sub.14, M.sub.21 -M.sub.24, . . . , M.sub.4m1 -M.sub.4m4 are connected to the terminals of the signal read lines S.sub.1, S.sub.2, . . . S.sub.16m, respectively.
Here, as an example, the horizontal scanning line l.sub.1 is commonly connected to the gate contacts of the switching transistors M.sub.11 -M.sub.14. Each of the horizontal scanning lines l.sub.1, l.sub.2, . . . l.sub.m has four switching transistors commonly connected thereto as a set through the gate contacts of the four switching transistors. First switching transistors of the respective sets of switching transistors (e.g., M.sub.11, M.sub.21, . . . ) are connected to a first output line 5; second switching transistors (e.g., M.sub.12, M.sub.22, . . . ) are connected to a second output line 6; third switching transistors (e.g., M.sub.13, M.sub.23, . . . ) are connected to a third output line 7; and fourth switching transistors (e.g., M.sub.14, M.sub.24, . . . ) are connected to a fourth output line 8; thereby outputting pixel signals S.sub.1 (.tau.), S.sub.2 (.tau.), S.sub.3 (.tau.), and S.sub.4 (.tau.) from the output lines 5, 6, 7, and 8 in parallel.
FIG. 6 shows a typical connection between the horizontal scanning line l.sub.1 and the first set of switching transistors M.sub.11 -M.sub.14, and the horizontal scanning line l.sub.2 and the second set of switching transistors M.sub.21 -M.sub.24.
The signal read lines S.sub.1 -S.sub.8 in the light receiving region is formed of a plurality of n.sup.+ -type impurity layers embedded in the p-type well layer, while the n.sup.+ -type impurity layers S.sub.1 '-S.sub.8 ' are embedded while separated at a predetermined interval from the terminals of the read line forming the n.sup.+ -type impurity layers. The N-channel MOS-type switching transistors M.sub.11 -M.sub.14 are formed by laminating the horizontal scanning line l.sub.1 (which is made of a polysilicon layer extending from the bit output contact h.sub.1 of the horizontal scanning circuit 3) on an upper surface stretching between the n.sup.+ -type impurity layers S.sub.1 -S.sub.4 and S.sub.1 '-S.sub.4 '. The N-channel MOS-type switching transistors M.sub.21 -M.sub.24 are formed by laminating the horizontal scanning line l.sub.2 (which is made of a polysilicon layer extending from the bit output h.sub.2 of the horizontal scanning circuit 3) on the upper surface stretching between the n.sup.+ -type impurity layers S.sub.5 -S.sub.8 and S.sub.5 '-S.sub.8 '.
The n.sup.+ -type impurity layers S.sub.1 ' and S.sub.5 ' are connected to the first output line 5 through contacts (designated by in the figure); the n.sup.+ -type impurity layers S.sub.2 ' and S.sub.6 ' are connected to the second output line 6 through contacts; the n.sup.+ -type impurity layers S.sub.3 ' and S.sub.7 ' are connected to the third output line 7 through contacts; and the n.sup.+ -type impurity layers S.sub.4 ' and S.sub.8 ' are connected to the fourth output line 8 through contacts. The output lines 5, 6, 7 and 8 are made of an aluminum layer.
Referring to FIG. 7, the solid-state imaging device having such a construction can read four pixel signals transmitted simultaneously as a set from the group of photodiodes to each signal read line. The four pixel signals are read in synchronism with the vertical scan timing of each signal S.sub.V1, S.sub.V2, S.sub.V3 . . . applied from the vertical scanning circuit 2 at a horizontal scanning period of the horizontal scanning circuit 3. Therefore, even if the horizontal scanning circuit 3 is not operated at high speeds, a substantially rapid scanning operation can still be achieved. Thus, this solid-state imaging devices can accommodate a large number of pixels.
Accordingly, the solid-state imaging device which horizontally scans a plurality of pixel signals simultaneously, as shown in FIG. 5, can read the pixel signals equivalent to each frame at high speeds, so that a plurality of frames can be formed into an image at high speeds. As an example, this device can be used to take the instantaneous motion of a rapidly changing object as a plurality of frames.
However, research and development has revealed that this device has the following problem that must be overcome. Specifically, when a horizontal scanning signal is applied sequentially from each bit output h.sub.1, h.sub.2 . . . h.sub.m of the horizontal scanning circuit 3 at a predetermined period .tau. during a horizontal scanning period so that four switching transistors grouped as a set corresponding to such bit output are caused to conduct and not to conduct sequentially for horizontal scanning, a voltage variation in the pixel signals of one set causes a voltage variation in the adjacent set due to inter-set capacitive coupling, thereby distorting the image.
This problem will be described in more detail with reference to FIG. 6. During a period in which the four pixel signals S.sub.1 (.tau.), S.sub.2 (.tau.), S.sub.3 (.tau.), and S.sub.4 (.tau.) are read in parallel by causing the first set of switching transistors M.sub.11 -M.sub.14 to conduct by a scanning signal from the first bit output h.sub.1 of the horizontal scanning circuit 3, the second set of switching transistors M.sub.21 -M.sub.24 located adjacent thereto do not conduct. By causing the first set of switching transistors M.sub.11 -M.sub.14 not to conduct and the second set of switching transistors M.sub.21 -M.sub.24 to conduct, the four pixel signals S.sub.1 (.tau.), S.sub.2 (.tau.), S.sub.3 (.tau.), and S.sub.4 (.tau.) corresponding to the second set of switching transistors are read in parallel. In such a case, as the drain regions (n.sup.+ impurity regions) S.sub.1 ', S.sub.2 ', S.sub.3 ', and S.sub.4 ' of the first set of switching transistors M.sub.11 -M.sub.14 are electrically initialized, their depletion layer capacitances are varied, thereby affecting the drain regions (n.sup.+ impurity regions) S.sub.5 ', S.sub.6 ', S.sub.7 ', and S.sub.8 ' of the second set of switching transistors M.sub.21 -M.sub.24 which is adjacently located. Thus, this variation in the depletion layer capacitance acts as a voltage variation when the second set of pixel signals is read.
The same phenomenon is observed every time other sets of pixel signals are scanned at the predetermined period .tau., thereby contaminating the image with noise.
Particularly, the pixel signals S.sub.3 (.tau.) and S.sub.4 (.tau.) passing through the switching transistors M.sub.14 and M.sub.21 (FIG. 6), which are most closely adjacent to each other among two adjacent sets of switching transistors, are most strongly affected, and as a result, vertically striped video noise is present in the reproduced image.
Further, such vertically striped video noise tends to increase with increasing the number of output lines to obtain rapid horizontal scanning and increasing the number of switching transistors within a set resulting from such increase in output lines.
That is, if the number of switching transistors in each set is increased, so is the number of switching transistors conducting and not conducting simultaneously every period .tau., and as a result, the capacitive coupling between any two adjacent sets is likewise increased. Thus, the negative influence brought about on the image quality by the capacitive variation is aggravated.